1. Field of the Invention
This invention relates to electronic packaging, and more particularly, to pin assignments for semiconductor chip packages.
2. Description of the Related Art
Levels of integration for semiconductor chips continue to increase. As a result of these increasing levels of integration, pin counts for semi-conductor packages continue to increase as well. Part of this increase is due to the additional signal connections that may be required. As the number of signal connections, and thus signal pins increases, the number of required power and ground pins on a semiconductor package increases as well. Power and ground pins may be necessary to ensure the integrity of signal passing through the signal pins of a semiconductor package. Power and ground pins may aid in providing low inductance current loops for signals. Power and ground pins may also aid in providing a relatively noise free return path for each signal.
In designing the packaging for a semiconductor chip, the total number of pins of may be determined by both the number of required signal connections, and a signal:power:ground ratio defined by a signal integrity engineer. This ratio is the number of signal pins to the number of power pins and number of ground pins. Thus, after determining the number of required signal pins, the minimum number of pins required for the semiconductor package may be determined using this ratio. Once the number of pins to be used by the semiconductor package has been determined, pin assignments may then be made. Typically, it is desirable to spread the power and ground pins equally throughout the distribution of pins.
One important factor that is typically not considered in the designing of the packaging for semiconductor chips is the routing of the signal paths for signal pins. Semiconductor packages are usually mounted to printed circuit boards (PCBs) or other type of carrier. The carrier may have multiple signal layers, and signal paths may be routed to these pins through these signal layers and vias, which pass through the signal layers to the pin of the semiconductor package. In some cases, the pin assignment may require the use of extra signal layers in order to ensure that paths (sometimes referred to as escape paths) are available for routing signal lines to the pins from other areas of the carrier.
The routing of signal lines may be further complicated by a small interconnect pitch that is required for many semiconductor packages (pitch is the distance between centers of signal pins). For example, for a PCB configured for the mounting of 1.27 mm (50 mil) pitch packages, 2 to 3 signal lines may be routed between interconnects on a single layer. On a PCB configured for the mounting of 1.0 mm (39 mil) packages, only 1-2 signal lines may be routed between interconnects on a single layer. Thus, as pitch decreases, it becomes more likely that extra signal layers will be required in order to provide escape paths for the routing of signal lines.
Extra signal layers may impose additional costs in the manufacture of PCB""s and other types of circuit carriers. Extra layers may result in higher material costs, as well as additional processing costs during manufacture. Furthermore, extra layers may provide more opportunities for defects to occur during manufacture, thereby adding additional costs that were not initially planned for. Extra layers may also lead to reliability issues during the operational life of the PCB. Thus, it is desirable to avoid the use of extra signal layers when routing signal paths to the pins of semiconductor packages.
A method for assigning power and ground pins in array packages in order to enhance next level routing is provided. In one embodiment, the method comprises arranging connections of a semiconductor array package, the semiconductor package having an integrated circuit with power, ground, and signal connections, in Mxc3x97N connection grids. In one embodiment, the grids are 2xc3x973 connection grids. Each connection grid includes a power connection and a ground connection which is adjacent to the power connection. The 2xc3x973 connection grids are arranged so that each connection at the periphery of the grid array for the entire package is a signal connection. A 4:1:1 signal:power:ground connection ratio is maintained in the arrangement, wherein no more than four signal connections are present for each power connection, and no more than four signal connections are present for each ground connection. Some no-connects (that is, pins with no electrical connection, or absence of pin in certain cells of the grid) may also be present to enhance signal routing.
The semiconductor package for which the arrangement is conducted may be an array package (e.g. a ball grid array) configured for mounting on a printed circuit board (PCB). A plurality of pads for mounting the semiconductor package may be located on the surface of the PCB. The PCB may also include a plurality of layers, including signal layers, one or more power planes, and one or more ground planes. Apertures in the planes, known as vias, may be used to connect power, ground or signals to the pads located on the PCB surface layer. Signal lines may be routed from pads associated with signal connections either on the surface of the PCB, or through a via to an internal layer. The arrangement of the connections on the semiconductor package may allow for more signal escape paths (i.e. paths for routing signal lines from the pads), which may result in fewer signal layers being necessary to implement the PCB.
Arrangement of the connections of a semiconductor array package by tiling the Mxc3x97N grids may ensure signal:power:ground ratio is achieved. Following the completion of the tiling, additional signal escape paths may be added by replacing some of the signal connections with no-connects. The method of arranging connections may be implemented manually by laying out the Mxc3x97N grids. It is further possible and contemplated that the tiling of the Mxc3x97N grids may be automated.
Thus, in various embodiments, the method for assigning power and ground pins may allow for additional signal routing escape paths. By allowing additional signal routing escape paths, fewer signal layers may be required to implement the PCB to which the semiconductor package is to be mounted. Using fewer signal layers may result in lower material and processing costs in the manufacture of the PCB.